Delay Calculation in Digital Design
In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above mentioned 2-D look up table (LUT). The idea behind semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip.
In this context, the blocks are logic gates such as NAND, OR, AND, etc. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc. The 2D table represents information about the variability of the gate's delay with respect to the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variable are called slew and load in design parlance.
A static timing analysis engine will first calculate the delay of the individual cells and string them together to do further analysis.
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