Placement
A transient load decoupling capacitor should usually be placed as close as possible to the device requiring the decoupled signal. The goal is to minimize the amount of line inductance and series resistance between the decoupling capacitor and that device, and the longer the conductor between the capacitor and the device, the more inductance there is.
The guidelines for placing a high-speed decoupling capacitor on a multi-layer printed circuit board depend on whether the board has dedicated power distribution planes and how closely spaced those planes are.
Since capacitors differ in their high-frequency characteristics (and capacitors with good high-frequency properties are often types with small capacity, while large capacitors usually have worse high-frequency response), decoupling often involves the use of a combination of capacitors. For example in logic circuits, a common arrangement is ~100 nF ceramic per logic IC (multiple ones for complex IC's), combined with electrolytic or tantalum capacitor(s) up to a few hundred μF per board / board section.
Read more about this topic: Decoupling Capacitor