CPU Design - Details

Details

CPU design focuses on these areas:

1. datapaths (such as ALUs and pipelines)
2. control unit: logic which controls the datapaths
3. Memory components such as register files, caches
4. Clock circuitry such as clock drivers, PLLs, clock distribution networks
5. Pad transceiver circuitry
6. Logic gate cell library which is used to implement the logic

CPUs designed for high-performance markets might require custom designs for each of these items to achieve frequency, power-dissipation, and chip-area goals.

CPUs designed for lower performance markets might lessen the implementation burden by:

• Acquiring some of these items by purchasing them as intellectual property
• Use control logic implementation techniques (logic synthesis using CAD tools) to implement the other components - datapaths, register files, clocks

Common logic styles used in CPU design include:

• Unstructured random logic
• Finite-state machines
• Microprogramming (common from 1965 to 1985)
• Programmable logic array (common in the 1980s, no longer common)

Device types used to implement the logic include:

• Transistor-transistor logic Small Scale Integration logic chips - no longer used for CPUs
• Programmable Array Logic and Programmable logic devices - no longer used for CPUs
• Emitter-coupled logic (ECL) gate arrays - no longer common
• CMOS gate arrays - no longer used for CPUs
• CMOS ASICs - what's commonly used today, they're so common that the term ASIC is not used for CPUs
• Field-programmable gate arrays (FPGA) - common for soft microprocessors, and more or less required for reconfigurable computing

A CPU design project generally has these major tasks:

• Programmer-visible instruction set architecture, which can be implemented by a variety of microarchitectures
• Architectural study and performance modeling in ANSI C/C++ or SystemC
• High-level synthesis (HLS) or RTL (e.g. logic) implementation
• RTL Verification
• Circuit design of speed critical components (caches, registers, ALUs)
• Logic synthesis or logic-gate-level design
• Timing analysis to confirm that all logic and circuits will run at the specified operating frequency
• Physical design including floorplanning, place and route of logic gates
• Checking that RTL, gate-level, transistor-level and physical-level representations are equivalent
• Checks for signal integrity, chip manufacturability

Re-designing a CPU core to a smaller die-area helps achieve several of these goals.

• Shrinking everything (a "photomask shrink"), resulting in the same number of transistors on a smaller die, improves performance (smaller transistors switch faster), reduces power (smaller wires have less parasitic capacitance) and reduces cost (more CPUs fit on the same wafer of silicon).
• Releasing a CPU on the same size die, but with a smaller CPU core, keeps the cost about the same but allows higher levels of integration within one VLSI chip (additional cache, multiple CPUs, or other components), improving performance and reducing overall system cost.

As with most complex electronic designs, the logic verification effort (proving that the design does not have bugs) now dominates the project schedule of a CPU.

Key CPU architectural innovations include index register, cache, virtual memory, instruction pipelining, superscalar, CISC, RISC, virtual machine, emulators, microprogram, and stack.