Computational Lithography - A Short History of Computational Lithography

A Short History of Computational Lithography

Computational Lithography means the use of computers to simulate printing of micro-lithography structures. Pioneering work was done by Chris Mack at NSA in developing PROLITH, Rick Dill at IBM and Andy Neureuther at Univ Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometres of resist. Commercial full-chip optical proximity correction, using model forms, was first implemented by TMA (now a subsidiary of Synopsys) and Numerical Technologies (also part of Synopsys) around 1997. Since then the market and complexity has grown significantly. With the move to sub-wavelength lithography at the 180 nm and 130 nm nodes, RET techniques such as Assist features, Phase Shift Masks started to be used together with OPC. For the transition from 65 nm to 45 nm nodes customers were worrying that not only that design rules were insufficient to guarantee printing without yield limiting hotspots, but also that tape-out time may need thousands of CPUs or weeks of run time. This predicted exponential increase in computational complexity for mask synthesis on moving to the 45 nm process node spawned a significant venture capital investment in Design for Manufacturing start-up companies. A number of startup companies promoting their own disruptive solutions to this problem started to appear, techniques from custom hardware acceleration to radical new algorithms such as Inverse Lithography were touted to resolve the forthcoming bottlenecks. Despite all this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML) in 2005 to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology. Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as Source Mask Optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major Mask Synthesis vendors have settled on the term "Computational Lithography" to describe and promote the set of Mask Synthesis technologies required for 22 nm.