Transmission Protocol
Camera Link uses one to three transceiver chips with four links at 7 serial bits each. At a minimum, Camera Link uses 28 bits to represent up to 24 bits of pixel data and 3 bits for video sync signals, leaving one spare bit. The video sync bits are Data Valid, Frame Valid, and Line Valid. The data are serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The receiver accepts the four LVDS data streams and LVDS clock, and then drives the 28 bits and a clock to the board. The camera link standard calls for these 28 bits to be transmitted over 4 serialized differential pairs with a serialization factor of 7. The parallel data clock is transmitted with the data. Typically a 7x clock must be generated by a PLL or SERDES block in order to transmit or receive the serialized video. To deserialize the data, a shift register and counter may be employed. The shift register catches each of the serialized bits, one at a time, then registers the data out into the parallel clock domain - once the data counter has reached its terminal value.
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