Pinout
| Pin Name | Pin Number(s) | Description |
|---|---|---|
| A0 - A15 | 13, 12, 11, 10, 28, 27, 26, 25, 24, 23, 16, 22, 17, 18, 19, 20 | Memory Address I/O |
| AN0 - AN2 | 2, 3, 5 | ANTIC Interface to CTIA/GTIA |
| D0 - D7 | 30, 31, 32, 33, 40, 39, 38, 37 | Data Bus I/O |
| FØ0 | 35 | Fast Phase 0 Input Clock |
| HALT | 9 | Halt Output, Suspends CPU while ANTIC reads memory |
| LP | 4 | Light Pen Imput |
| NMI | 7 | NMI Interrupt Output to CPU |
| RDY | 15 | Ready Output. ANTIC pulls pin low to halt the CPU for horizontal blank syncing (WSYNC) |
| REF | 8 | RAM Refresh Output |
| RNMI | 6 | NMI Interrupt Input |
| RST | 36 | Reset ANTIC Input |
| R/W | 14 | Read/Write I/O direction |
| Vcc | 21 | Power +5 Volts |
| Vss | 1 | Ground |
| Ø0 | 34 | Phase 0 Clock Output |
| Ø2 | 29 | Phase 2 Input Clock |
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