Wiggler (JTAG) - Example: ARM11 Debug TAP

Example: ARM11 Debug TAP

A concrete example will help show the way JTAG works in real systems. The example here is the debug TAP of an ARM11 processor, the ARM1136 core. The processor itself has extensive JTAG capability, similar to what is found in other CPU cores, and it's integrated into chips with even more extensive capabilities accessed through JTAG.

So this is a non-trivial example, which is representative of a significant cross section of JTAG-enabled systems. In addition, it shows how control mechanisms are built using JTAG's register read/write primitives, and how those combine to facilitate testing and debugging complex logic elements; CPUs are common, but FPGAs and ASICs include other complex elements which need to be debugged.

Licensees of this core integrate it into chips, usually combining it with other TAPs as well as numerous peripherals and memory. (Peripherals and memory comprise the bulk of SoC designs; ARM cores don't take up much chip area.) One of those other TAPs will handle boundary scan testing for the whole chip; it is not supported by the debug TAP. Examples of such chips include:

• The OMAP2420, which includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine, with the boundary scan TAP ("ICEpick-B") having the ability to splice TAPs into and out of the JTAG scan chain.
• The i.MX31 processor, which is similar, although its "System JTAG" boundary scan TAP, which is very different from ICEpick, and it includes a TAP for its DMA engine instead of a DSP and imaging engine.

Those processors are both intended for use in wireless handsets such as cell phones, which is part of the reason they include TAP controllers which modify the JTAG scan chain: Debugging low power operation requires accessing chips when they are largely powered off, and thus when not all TAPs are operational. That scan chain modification is one subject of a forthcoming IEEE 1149.7 standard.