General Information
Compared to other CAD systems, TopoR dramatically reduces the total wire length and number of vias. TopoR successfully routes both single-layer and high-density multilayer boards.
Routing of the wiring topology is done automatically and flexibly; angles are not limited to 90° and 45°.
Efficient use of PCB space and absence of preferred routing directions in layers considerably reduces electromagnetic crosstalks.
TopoR routes all connections, even if this entails violating design constraints. Such violations can be automatically corrected later. On densely-packed boards this feature is crucial, because it helps assess both the possibility and workload for manual adjustments.
When you move objects (such as components and vias) around, wire length and shape are optimized automatically with appropriate clearance. This considerably simplifies the process of editing without making you care about observing design constraints.
The user is free to choose from two ways to calculate the wire shape: with or without arcs. The first method involves wires consisting of lines only. The other makes wires keep appropriate clearance when circling pads and consist of arcs and lines.
TopoR simultaneously optimizes several alternative variants of the layout. Variants with the worst parameters (total wire length and number of vias) will be removed. This approach allows the distributed routing mechanism to be used, which improves the speed of routing. According to the authors of TopoR, distributed routing will be available in a future release.
TopoR has an automatic component placement feature. The procedure can be used both for all components of the board and only for components in a specific area. It is not comparable to the quality of the manual placement, but it can be used as a preparation step for manual placement.
The minimum and desired clearances for each net can be specified.
TopoR automatically reduces the width of a wire that approaches a narrow pad (or one with a diameter that is less than the width of the wire), or when it passes through bottlenecks (for example, between the pads of a component).
Wire-to-pad transitions use teardrop-style smoothing. The use of this procedure at the design stage helps avoid violations in design-rule checking when teardrops are added in the CAM editor.
TopoR can recognize BGA (Ball Grid Array) component areas and apply a special strategy for routing them. This helps reduce the number of vias, the density of connections, and in some cases the number of routing layers.
TopoR is very effective for routing single-layer printed circuit boards, because it guarantees (within a particular layout) the absolute minimum of vias. During routing, TopoR either finds a single-layer solution or an alternative with as few vias as possible.
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