Time To Digital Converter - Utilities

Utilities

A flip flop can be used to convert pulses into edges and vice versa.

A gate has an analog and a logic input. When the logic input is low, the output is zero. A typical sampling pulse of 1 ns width and a 1Msamples ADC and a signal-to-noise ratio of 100 means that the analog signal has to be suppressed by a factor of 100000 (low leakage). If the gate is used in conjunction with an integrator, the transmission should be constant over the integration interval within 0.001.

In a sampling oscilloscope an edge of a signal is sharpened by a diode pair, then fed through a delay generator, then converted into a pulse, and then gates the signal. The output of the gate is held in a capacitor and converted by an ADC. A multi-channel analyzer derives the gate pulse from a const-fraction discriminator and uses a fixed delay for a third copy of the original signal to account for the delay in the discriminator. If a series of gates is opened in a short sequence, the pulse shape can be sampled. No const-fraction discriminator is needed then and the system is very flexible concerning the pulse shape.

Often the sampled charge could be stored in the capacitor formed by the gate and channel of a MOSFET. The any current drawn by the ADC will not reduce the charge. Furthermore by drawing the current a long time a large charge amplification is possible. This is called a sample and hold circuit or also a track and hold circuit. The binary variant is called a buffer.