TI MSP430 - Peripherals - Integrated Peripherals

Integrated Peripherals

Analog

• Analog-to-Digital Converter

The MSP430 line offers two types of Analog-to-Digital Conversion (ADC). 10- and 12-bit Successive Approximation converters, as well as a 16-bit Sigma-Delta converter. Data transfer controllers and a 16 word conversion-and-control buffer allow the MSP430 to convert and store samples without CPU intervention, minimizing power consumption.

• Analog Pool

The Analog Pool (A-POOL) module can be configured as an ADC, DAC, Comparator, SVS or temperature sensor. It allows flexibility for the user to program a series of analog functions with only one setup.

• Comparator A, A+

The MSP430's comparator module provides precision slope Analog-to-Digital Conversions. Monitors external analog signals and provides voltage and resistor value measurement. Capable of selectable power modes.

• DAC12

The DAC12 module is a 12-bit, voltage-output DAC featuring internal/external reference selection and programmable settling time for optimal power consumption. It can be configured in 8- or 12-bit mode. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.

• Op Amps

Feature single supply, low current operation with rail-to-rail outputs and programmable settling times. Software selectable configuration options: unity gain mode, comparator mode, inverting PGA, non-inverting PGA, differential and instrumentation amplifier.

• Sigma Delta (SD)

The SD16/SD16_A/SD24_A modules each feature 16-/24-bit sigma-delta A/D converters with an internal 1.2-V reference. Each converter has up to eight fully differential multiplexed inputs, including a built-in temperature sensor. The converters are second-order oversampling sigma-delta modulators with selectable oversampling ratios of up to 1024 (SD16_A/SD24_A) or 256 (SD16).

Timers

• Basic Timer (BT)

The BT has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The BT is extended to provide an integrated RTC. An internal calendar compensates for months with less than 31 days and includes leap-year correction.

• Real-Time Clock

RTC_A/B are 32-bit hardware counter modules that provide clock counters with a calendar, a flexible programmable alarm, and calibration. The RTC_B includes a switchable battery backup system that provides the ability for the RTC to operate when the primary supply fails.

• 16-bit Timers

Timer_A, Timer_B and Timer_D are asynchronous 16-bit timers/counters with up to seven capture/compare registers and various operating modes. The timers support multiple capture/compares, PWM outputs, and interval timing. They also have extensive interrupt capabilities. Timer_B introduces additional features such as programmable timer lengths (8, 10, 12 or 16-bit), while Timer_D introduces a high-resolution mode (4ns resolution).

• Watchdog (WDT+)

The WDT+ performs a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

System

• Advanced Encryption Standard (AES)

The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the advanced encryption standard in hardware, and can be configured with user software.

• Brown-Out Reset (BOR)

The BOR circuit detects low supply voltages and resets the device by triggering a power-on reset (POR) signal when power is applied or removed. The MSP430 MCU’s zero-power BOR circuit is continuously turned on, including in all low-power modes.

• Direct Memory Access (DMA) Controller

The DMA controller transfers data from one address to another across the entire address range without CPU intervention. The DMA increases the throughput of peripheral modules and reduces system power consumption. The module features up to three independent transfer channels.

Although the MSP430's DMA subsystem is very capable it has several flaws, the most significant of which is the lack of an external transfer strobe. Although a DMA transfer can be triggered externally, there is no external indication of completion of a transfer. Consequently DMA to and from external sources is limited to external trigger per byte transfers, rather than full blocks automatically via DMA. This can lead to significant complexity (as in requiring extensive hand tweaking of code) when implementing processor to processor or processor to USB communications. The reference cited uses an obscure timer mode to generate high speed strobes for DMA transfers. Unfortunately, the timers are not flexible enough to easily make up for the lack of an external DMA transfer strobe.

DMA operations that involve word transfers to byte locations cause truncation to 8 bits rather than conversion to two byte transfers. This makes DMA with A/D or D/A 16 bit values less useful than it could be (although it is possible to DMA these values through port A or B on some versions of the MSP 430 using an externally visible trigger per transfer such as a timer output).

• Enhanced Emulation Module (EEM)

The EEM provides different levels of debug features such as 2-8 hardware breakpoints, complex breakpoints, break when read/write occurs at specified address, and more. Embedded into all flash-based MSP430 devices.

• Hardware multiplier

Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations. Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch. This peripheral does not interfere with CPU activities and can be accessed by the DMA. The MPY on all MSP430F5xx and some MSP430F4xx devices feature up to 32-bit x 32-bit.

The 8 registers used are:

Address	Name	Function
0x130	MPY	Operand1 for unsigned multiply
0x132	MPYS	Operand1 for signed multiply
0x134	MAC	Operand1 for unsigned multiply-accumulate
0x136	MACS	Operand1 for signed multiply-accumulate
0x138	OP2	Second operand for multiply operation
0x13A	ResLo	Low word of multiply result
0x13C	ResHi	High word of multiply result
0x13E	SumExt	Carry out of multiply-accumulate

The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.

If a multiply-accumulate operation is desired, the ResLo and ResHi registers must also be initialized.

Then, each time a write is performed to the OP2 register, a multiply is performed and the result stored or added to the result registers. The SumExt register is a read-only register that contains the carry out of the addition (0 or 1) in case of an unsigned multiply), or the sign extension of the 32-bit sum (0 or -1) in case of a signed multiply. In the case of a signed multiply-accumulate, the SumExt value must be combined with the most significant bit of the prior SumHi contents to determine the true carry out result (-1, 0, or +1).

The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.

• Memory Protection Unit (MPU)

The FRAM MPU protects against accidental writes to designated read-only memory segments or execution of code from a constant memory. The MPU can set any portioning of memory with bit level addressing, making the complete memory accessible for read, write and execute operations in FRAM devices.

• Power Management Module (PMM)

The PMM generates a supply voltage for the core logic, and provides several mechanisms for the supervision and monitoring of both the voltage applied to the device and the voltage generated for the core. It is integrated with a low-dropout voltage regulator (LDO), brown-out reset (BOR), and a supply voltage supervisor and monitor.

• Supply-Voltage Supervisor (SVS)

The SVS is a configurable module used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a power-on reset (POR) when the supply voltage or external voltage drops below a user-selected threshold.

Communication and Interface

• Capacitive Touch Sense I/Os

The integrated capacitive touch sense I/O module offers several benefits to touch button and touch slider applications. The system does not require external components to create the self-oscillation (reducing bill of materials) and the capacitor (that defines the frequency of the self-oscillation) can be connected directly. In addition, there is no need for external MUXes to allow multiple pads and each I/O pad can directly serve as a cap sense input. A hysteresis of ~0.7V ensures robust operation. Control and sequencing is done completely in software.

• General Purpose I/Os

MSP430 devices have up to 12 digital I/O ports implemented. Each port has eight I/O pins. Every I/O pin can be configured as either input or output, and can be individually read or written to. Ports P1 and P2 have interrupt capability. MSP430F2xx, F5xx and some F4xx devices feature built-in, individually configurable pull-up or pull-down resistors.

• Sub-GHZ RF Front End

The flexible CC1101 sub-1GHz transceiver delivers the sensitivity and blocking performance required to achieve successful communication links in any RF environment. It also features low current consumption and supports flexible data rates and modulation formats.

• USART (UART, SPI, I²C)

The universal synchronous/asychrnous receive/transmit (USART) peripheral interface supports asynchronous RS-232 and synchronous SPI communication with one hardware module. The MSP430F15x/16x USART modules also support I²C, programmable baud rate, and independent interrupt capability for receive and transmit.

• USB

The USB module is fully compliant with the USB 2.0 specification and supports control, interrupt and bulk transfers at a data rate of 12 Mbps (full speed). The module supports USB suspend, resume and remote wake-up operations and can be configured for up to eight input and eight output endpoints. The module includes an integrated physical interface (PHY); a phase-locked loop (PLL) for USB clock generation; and a flexible power-supply system enabling bus-powered and self-powered devices.

• USCI (UART, SPI, I²C, LIN, IrDA)

The universal serial communication interface (USCI) module features two independent channels that can be used simultaneously. The asynchronous channel (USCI_A) supports UART mode; SPI mode; pulse shaping for IrDA; and automatic baud-rate detection for LIN communications. The synchronous channel (USCI_B) supports I²C and SPI modes.

• USI (SPI, I²C)

The universal serial interface (USI) module is a synchronous serial communication interface with a data length of up to 16-bits and can support SPI and I²C communication with minimal software.

Metering

• ESP430 (integrated in FE42xx devices)

The ESP430CE module performs metering calculations independent of the CPU. Module has separate SD16, HW multiplier, and the ESP430 embedded processor engine for single-phase energy-metering applications.

• Scan Interface (SIF)

The SIF module, a programmable state machine with an analog front end, is used to automatically measure linear or rotational motion with the lowest possible power consumption. The module features support for different types of LC and resistive sensors and for quadrature encoding.

Display

• LCD/LCD_A/LCD_B

The LCD/LCD_A controller directly drives LCDs for up to 196 segments. Supports static, 2-mux, 3-mux, and 4-mux LCDs. LCD_A module has integrated charge pump for contrast control. LCD_B enables blinking of individual segments with separate blinking memory.