Three-dimensional Integrated Circuit - Benefits

Benefits

Traditional scaling of semiconductor chips also improves signal propagation speed. However, scaling from current manufacturing and chip-design technologies has become more difficult, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do 3-D integrated circuits were proposed invented to address the scaling challenge by stacking 2-D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout. 3D ICs promise many significant benefits, including:

Footprint

More functionality fits into a small space. This extends Moore's law and enables a new generation of tiny but powerful devices.

Cost

Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.

Heterogeneous integration

Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.

Shorter interconnect

The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.

Power

Keeping a signal on-chip can reduce its power consumption by 10–100 times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.

Design

The vertical dimension adds a higher order of connectivity and offers new design possibilities.

Circuit security

The stacked structure complicates attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.

Bandwidth

3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.