Static Timing Analysis - Purpose

Purpose

In a synchronous digital system, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock. Only two kinds of timing errors are possible in such a system:

• A hold time violation, when an input signal changes too quickly, after the clock's active transition
• A setup time violation, when a signal arrives too late, and misses the time when it should advance.

The time when a signal arrives can vary due to many reasons - the input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured.

Since STA is capable of verifying every path, it can detect other problems like glitches, slow paths and clock skew.