SSE5 Enhancements
The proposed SSE5 instruction set consisted of 170 instructions (including 46 base instructions), many of which are designed to improve single-threaded performance. Some SSE5 instructions are 3-operand instructions, the use of which will increase the average number of instructions per cycle achievable by x86 code. Selected new instructions include:
- Fused multiply–accumulate (FMACxx) instructions
- Integer multiply–accumulate (IMAC, IMADC) instructions
- Permutation (PPERM, PERMPx) and conditional move (PCMOV) instructions
- Precision control, rounding, and conversion instructions
AMD claims SSE5 will provide dramatic performance improvements, particularly in high-performance computing (HPC), multimedia, and computer security applications, including a 5x performance gain for Advanced Encryption Standard (AES) encryption and a 30% performance gain for discrete cosine transform (DCT) used to process video streams.
For more detailed information, consult the instruction sets as subsequently divided.
- XOP: A revision of most of the SSE5 instruction set
- FMA4: Floating-point vector multiply–accumulate.
- F16C: Half-precision floating-point conversion.
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