Core Comparison
Processor | Developer | Open Source | Bus Support | Notes | Project Home |
---|---|---|---|---|---|
TSK3000A | Altium | No Royalty-Free | Wishbone | 32-bit R3000 style RISC Modified Harvard Architecture CPU | Embedded Design on Altium Wiki |
TSK51/52 | Altium | No Royalty-Free | Wishbone / Intel 8051 | 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative | Embedded Design on Altium Wiki |
OpenSPARC T1 | Sun | Yes | 64-bit | OpenSPARC.net | |
MicroBlaze | Xilinx | No | PLB, OPB, FSL, LMB, AXI4 | Xilinx MicroBlaze | |
PicoBlaze | Xilinx | Yes | Xilinx PicoBlaze | ||
Nios, Nios II | Altera | No | Avalon | Altera Nios II | |
Cortex-M1 | ARM | No | |||
eSi-RISC | EnSilica | No | AMBA AXI, AHB and APB | Configurable as 16 or 32-bit. Supports ASIC and FPGA. | EnSilica eSi-RISC |
LatticeMico32 | Lattice | Yes | Wishbone | LatticeMico32 | |
LEON2(-FT) | ESA | Yes | AMBA2 | SPARC V8 | ESA |
LEON3/4 | Aeroflex Gaisler | Yes | AMBA2 | SPARC V8 | Aeroflex Gaisler |
Navré | Sébastien Bourdeauducq | Yes | Direct SRAM | Atmel AVR compatible 8-bit RISC | Project page at Opencores |
OpenRISC | OpenCores | Yes | Wishbone | 32-bit; Done in ASIC, Actel, Altera, Xilinx FPGA | OR1K |
ARC | ARC International, Synopsys | No | 16/32-bit ISA RISC | DesignWare ARC | |
pAVR | Doru Cuturela | Yes | Atmel AVR compatible 8-bit RISC | Project page at Opencores | |
AEMB | Shawn Tan | Yes | Wishbone | MicroBlaze EDK 3.2 compatible Verilog core | AEMB |
OpenFire | Virginia Tech CCM Lab | Yes | OPB, FSL | Binary compatible with the MicroBlaze | |
SecretBlaze | LIRMM, University of Montpellier / CNRS | Yes | Wishbone | MicroBlaze ISA, VHDL | SecretBlaze |
SYNPIC12 | Miguel Angel Ajo Pelayo | Yes MIT | PIC12F compatible, program synthesised in gates | nbee.es | |
PacoBlaze | Pablo Bleyer | Yes | Compatible with the PicoBlaze processors | PacoBlaze | |
CPU86 | HT-Lab | Yes | 8088 compatible CPU in VHDL | cpu86 | |
xr16 | Jan Gray | No | XSOC abstract bus | 16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118 | XSOC/xr16 |
JOP | Martin Schoeberl | Yes | SimpCon / Wishbone (extension) | Stack oriented, hard real-time support, executes Java bytecode directly | Jop |
ERIC5 | Entner Electronics | No | 9-bit RISC, very small size, C-programmable | ERIC5 | |
YASEP | Yann Guidon | Yes AGPLv3 | Direct SRAM | 16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready | yasep.org (Firefox required) |
Zet | Zeus Gómez Marmolejo | Yes | Wishbone | x86 PC clone | Zet |
ZPU | Zylin AS | Yes | Wishbone | Stack based CPU, configurable 16/32 bit datapath, eCos support | Zylin CPU |
Read more about this topic: Soft Microprocessor
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