Signal Integrity - On-chip Signal Integrity

On-chip Signal Integrity

Signal integrity problems in modern integrated circuits (ICs) can have many drastic consequences for digital designs:

• Products can fail to operate at all, or worse yet, become unreliable in the field.
• The design may work, but only at speeds slower than planned
• Yield may be lowered, sometimes drastically

The cost of these failures is very high, and includes photomask costs, engineering costs and opportunity cost due to delayed product introduction. Therefore electronic design automation (EDA) tools have been developed to analyze, prevent, and correct these problems. In integrated circuits, or ICs, the main cause of signal integrity problems is crosstalk. In CMOS technologies, this is primarily due to coupling capacitance, but in general it may be caused by mutual inductance, substrate coupling, non-ideal gate operation, and other sources. The fixes normally involve changing the sizes of drivers and/or spacing of wires.

In analog circuits, designers are also concerned with noise that arise from physical sources, such as thermal noise, flicker noise, and shot noise. These noise sources on the one hand present a lower limit to the smallest signal that can be amplified, and on the other, define an upper limit to the useful amplification.

In digital ICs, noise in a signal of interest arises primarily from coupling effects from switching of other signals. Increasing interconnect density has led to each wire having neighbors that are physically closer together, leading to increased coupling capacitance between neighboring nets. As circuits have continued to shrink in accordance with Moore's law, several effects have conspired to make noise problems worse:

• To keep resistance tolerable despite decreased width, modern wire geometries are thicker in proportion to their spacing. This increases the sidewall capacitance at the expense of capacitance to ground, hence increasing the induced noise voltage (expressed as a fraction of supply voltage).
• Technology scaling has led to lower threshold voltages for MOS transistors, and has also reduced the difference between threshold and supply voltages, thereby reducing noise margins.
• Logic speeds, and clock speeds in particular, have increased significantly, thus leading to faster transition (rise and fall) times. These faster transition times are closely linked to higher capacitive crosstalk. Also, at such high speeds the inductive properties of the wires come into play, especially mutual inductance.

These effects have increased the interactions between signals and decreased the noise immunity of digital CMOS circuits. This has led to noise being a significant problem for digital ICs that must be considered by every digital chip designer prior to tape-out. There are several concerns that must be mitigated:

• Noise may cause a signal to assume the wrong value. This is particularly critical when the signal is about to be latched (or sampled), for a wrong value could be loaded into a storage element, causing logic failure.
• Noise may delay the settling of the signal to the correct value. This is often called noise-on-delay.
• Noise (e.g. ringing) may cause the input voltage of a gate to drop below ground level, or to exceed the supply voltage. This can reduce the lifetime of the device by stressing components, induce latchup, or cause multiple cycling of signals that should only cycle once in a given period.