Technical Specification
The first Indigo, code-named "Hollywood", was introduced on 22 July 1991. It was based on the IP12 processor board, which contained a 32-bit MIPS R3000A microprocessor soldered on the board and proprietary memory slots supporting up to 96 MB of RAM.
The later version (codename Blackjack) was based on the IP20 processor board, which had a removable processor module (PM1 or PM2) containing a 64-bit MIPS R4000 (100 MHz) or R4400 processor (100 MHz or 150 MHz) that implemented the MIPS-III instruction set. The IP20 used standard 72-pin SIMMs with parity, and had 12 SIMM slots for a total of 384 MB of RAM at maximum.
A Motorola 56000 DSP was used for Audio IO. Ethernet is supported onboard by the SEEQ 80c03 chipset coupled with the HPC (High-performance Peripheral Controller), which provides the DMA engine. The HPC interfaces primarily between the GIObus and the Ethernet, SCSI (wd33c93 chipset) and the 56000 DSP. The GIO bus interface is implemented by the PIC (Processor Interface Controller) on IP12 and MC (Memory Controller) on IP20.
Much of the hardware design can be traced back to the 4D/3x series, which shares the same memory controller, Ethernet, SCSI, and optionally DSP as the IP12 Indigo. Indeed, the 4D/30, 4D/35 and Indigo R3000 are all considered IP12 machines and run the same IRIX kernel. The Indigo R3000 is effectively a reduced cost 4D/35 without a VME bus. The PIC supports a VME expansion bus (used on the 4D/3x series) and GIO expansion slots (used on the Indigo). In all IP12, IP20, and IP22/IP24 (see SGI Indigo2) systems the HPC attaches to the GIO bus.
Read more about this topic: SGI Indigo
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