The Standard
The standard defines two interface levels; the physical level that deals with electrical signals, connectors, mechanical and thermal conditions and the logical level that describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives, control and status registers, and initialization and error recovery facilities. This structure allows new developments in physical interface technology to be easily adapted without any redesign on the logical level.
Support for large systems (scalability) is achieved through a distributed directory based cache coherence model. (The other popular models for cache coherency are based on system-wide eavesdropping (snooping) of memory transactions – a scheme which is not very scalable.) In SCI each node contains a directory with a pointer to the next node in a linked list that shares a particular cache line.
SCI defines a 64-bit flat address space (16 exabytes) where 16 bits are used for identifying a node (64k, i.e. 65 536 nodes) and 48 bits for address within the node (256 terabytes). A node can contain many processors and/or memory. The SCI standard defines a packet switched network.
Read more about this topic: Scalable Coherent Interface
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