Packaging
RF MEMS components are fragile and require wafer level packaging or single chip packaging which allow for hermetic cavity sealing. A cavity is required to allow movement, whereas hermeticity is required to prevent cancellation of the spring force by the Van der Waals force exerted by water droplets and other contaminants on the beam. RF MEMS switches, switched capacitors and varactors can be packaged using wafer level packaging. Large monolithic RF MEMS filters, phase shifters, and tunable matching networks require single chip packaging.
Wafer-level packaging is implemented before wafer dicing, as shown in Fig. 3(a), and is based on anodic, metal diffusion, metal eutectic, glass frit, polymer adhesive, and silicon fusion wafer bonding. The selection of a wafer-level packaging technique is based on balancing the thermal expansion coefficients of the material layers of the RF MEMS component and those of the substrates to minimize the wafer bow and the residual stress, as well as on alignment and hermeticity requirements. Figures of merit for wafer-level packaging techniques are chip size, hermeticity, processing temperature, (in)tolerance to alignment errors and surface roughness. Anodic and silicon fusion bonding do not require an intermediate layer, but do not tolerate surface roughness. Wafer-level packaging techniques based on a bonding technique with a conductive intermediate layer (conductive split ring) restrict the bandwidth and isolation of the RF MEMS component. The most common wafer-level packaging techniques are based on anodic and glass frit wafer bonding. Wafer-level packaging techniques, enhanced with vertical interconnects, offer the opportunity of three-dimensional integration.
Single-chip packaging, as shown in Fig. 3(b), is implemented after wafer dicing, using pre-fabricated ceramic or organic packages, such as LCP injection molded packages or LTCC packages. Pre-fabricated packages require hermetic cavity sealing through clogging, shedding, soldering or welding. Figures of merit for single-chip packaging techniques are chip size, hermeticity, and processing temperature.
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