CPU Addressing Limits
For performance reasons, all the parallel address lines of an address bus must be valid at the same time, otherwise access to memory would be delayed and performance would be seriously reduced. Integrated circuit packages may have a limit on the number of pins available to provide the memory bus. Different versions of a CPU architecture, in different-sized IC packages, can be designed, trading off reduced package size for reduced pin count and address space. A trade-off might be made between address pins and other functions, restricting the memory physically available to an architecture even if it inherently has a higher capacity. On the other hand, segmented or bank switching designs provide more memory address space than is available in an internal memory address register.
As integrated circuit memory became less costly, it was feasible to design systems with larger and larger physical memory spaces.
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