Physical Description
The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of an instruction-cache unit (ICU), a fixed-point unit (FXU), a floating point unit (FPU), a number of data-cache units (DCU), a storage-control unit (SCU) and a I/O unit. Due to its modular design, IBM was able to create two cofigurations by simply varying the number of DCUs, RIOS-1 and a RIOS.9. The RIOS-1 configuration has four DCUs, the intended amount, and was clocked at up to 40 MHz, whereas the RIOS.9 CPU had two DCUs and was clocked at lower frequencies.
The chips are mounted on the “CPU planar”, a printed circuit board (PCB), using through-hole technology. Due to the large number of chips with wide buses, the PCB has eight planes for routing wires, four for power and ground and four for signals. There are two signal planes on each side of the board, while the four power and ground planes are in the center.
The chips that make up the POWER1 is fabricated in a 1.0 µm CMOS process with three layers of interconnect. The chips are packaged in ceramic pin grid array (CPGA) packages that can have up to 300 pins and dissipate a maximum of 4 W of heat each. The total number of transistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.9 million, with 2.04 million used for logic and 4.86 million used for memory. The die area of all the chips combined is 1,284 mm². The total number of signal pins is 1,464.
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