PIC Microcontroller - Family Core Architectural Differences - PIC24 and DsPIC 16-bit Microcontrollers

PIC24 and DsPIC 16-bit Microcontrollers

In 2001, Microchip introduced the dsPIC series of chips, which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.

Although still similar to earlier PIC architectures, there are significant enhancements:

• All registers are 16 bits wide
• Data address space expanded to 64 Kbytes
• First 2K is reserved for peripheral control registers
• Data bank switching is not required unless RAM exceeds 62K
• "f operand" direct addressing extended to 13 bits (8 Kbytes)
• 16 W registers available for register-register operations.

(But operations on f operands always reference W0.)

• Program counter is 22 bits (Bits 22:1; bit 0 is always 0)
• Instructions are 24 bits wide
• Instructions come in byte (B=1) and (16-bit) word (B=0) forms
• Stack is in RAM (with W15 as stack pointer); there is no hardware stack
• W14 is the frame pointer
• Data stored in ROM may be accessed directly ("Program Space Visibility")
• Interrupt vectors for different interrupt sources are supported.

Some features are:

• hardware MAC (multiply–accumulate)
• barrel shifting
• bit reversal
• (16×16)-bit single-cycle multiplication and other DSP operations
• hardware divide assist (19 cycles for 16/32-bit divide)
• hardware support for loop indexing
• Direct memory access

dsPICs can be programmed in C using Microchip's C30 compiler which is a variant of GCC.

Instruction ROM is 24 bits wide. Software can access ROM in 16-bit words, where even words hold the least significant 16 bits of each instruction, and odd words hold the most significant 8 bits. The high half of odd words reads as zero. The program counter is 23 bits wide, but the least significant bit is always 0, so there are 22 modifiable bits.

Instructions come in 2 main varieties. One is like the classic PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped. so the f operand may be any W register,

The other form, new to the PIC24, specifies 3 W register operands, 2 of which allow a 3-bit addressing mode specification:

The register offset addressing mode is only available to 2-operand instructions. 3-operand instructions use Ww as the second source operand, and use this encoding for an unsigned 5-bit immediate source. Note that the same Ww may be added to both Wd and Ws.

A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.