Phase-change Memory - PRAM Vs. Flash

PRAM Vs. Flash

It is the switching time and inherent scalability that makes PRAM most appealing. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.

Flash memory works by modulating charge (electrons) stored within the gate of a MOS transistor. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in insulator "traps"). The presence of charge within the gate shifts the transistor's threshold voltage, higher or lower, corresponding to a 1 to 0, for instance. Changing the bit's state requires removing the accumulated charge, which demands a relatively large voltage to "suck" the electrons off the floating gate. This burst of voltage is provided by a charge pump, which takes some time to build up power. General write times for common Flash devices are on the order of 0.1ms (for a block of data), about 10,000 times the typical 10 ns read time, for SRAM for example (for a byte).

PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times faster than conventional hard drives, makes it particularly interesting in nonvolatile memory roles that are currently performance-limited by memory access timing.

In addition, with Flash, each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are rated for, currently, only 5,000 writes per sector, and many flash controllers perform wear leveling to spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than Flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles. PRAM lifetime is limited by mechanisms such as degradation due to GST thermal expansion during programming, metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being soldered on to a board, or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see reflow soldering or wave soldering). This is made worse by the recent drive to lead-free manufacturing requiring higher soldering temperatures. The manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.

The special gates used in Flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The resistivity of the memory element in PRAM is more stable; at the normal working temperature of 85°C, it is projected to retain data for 300 years.

By carefully modulating the amount of charge stored on the gate, Flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles the memory density, reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent advances have removed this problem.

Because Flash devices trap electrons to store information, they are susceptible to data corruption from radiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode or a BJT provides the greatest amount of current for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. The chalcogenide resistance being a necessarily larger resistance than the diode entails that the operating voltage must exceed 1 V by a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the total reverse bias leakage current from the unselected bit lines. In transistor-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete dopants as the p-n junction width scales down.