Phase-change Memory - Challenges

Challenges

The greatest challenge for phase-change memory has been the requirement of high programming current density (>107 A/cm², compared to 105-106 A/cm² for a typical transistor or diode) in the active volume highly unlikely. This has led to active areas that are much smaller than the driving transistor area. The discrepancy has forced phase-change memory structures to package the heater and sometimes the phase-change material itself in sublithographic dimensions. This is a process cost disadvantage compared to Flash.

The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions that allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.

Probably the biggest challenge for phase change memory is its long-term resistance and threshold voltage drift. The resistance of the amorphous state slowly increases according to a power law (~t0.1). This severely limits the ability for multilevel operation (a lower intermediate state would be confused with a higher intermediate state at a later time) and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

In April 2010, Numonyx released its Omneo line of parallel and serial interface 128 Mb NOR-Flash replacement PRAM chips. Although the NOR flash chips they intended to replace operated in the -40-85 °C range, the PRAM chips operated in the 0-70°C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature sensitive p-n junctions to provide the high currents needed for programming.