PA-8500
The PA-8500 (PCX-W), code-named Vulcan, is a further development of the PA-8200. It taped-out in early 1998 and was introduced in late-1998 within systems. Production versions operated at frequencies of 300 to 440 MHz, but it was designed to, and has, operated up to 500 MHz. The most notable improvements are the higher operating frequencies and the on-die integration of the primary caches. The higher operating frequencies and the integration of the primary caches on the same die as the core was enabled by the migration to a 0.25 µm process. The PA-8200 core measured 10.8 mm by 11.4 mm (123.12 mm2) in the new process, less than half the area of the 0.5 µm PA-8200. This made area available that could be used for integrating the caches.
The PA-8500 has a 512 KB instruction cache and a 1 MB data cache. Other improvements to the microarchitecture include a larger BHT containing 2,048 entries, twice the capacity of the PA-8200's, and a larger TLB containing 160 entries. The PA-8500 uses a new version of the Runway bus. The new version operates at 125 MHz and transfers data on both rising and falling edges of the clock signal (double data rate, or DDR) and yields 240 MT/s or 2 GB/s of bandwidth. As the Runway bus is used to transfer addresses and data, usable bandwidth is 80% that of 2 GB/s, or around 1.6 GB/s.
The PA-8500 contains 140 million transistors and measures 21.3 mm by 22.0 mm (468.6 mm2). It was fabricated by Intel Corporation in a 0.25 µm CMOS process with five levels of aluminium interconnect. It uses a 2.0 V power supply. HP did not fabricate the PA-8500 themselves as they had ceased to upgrade their fabs to implement a process newer than CMOS-14C, which was used to fabricate previous PA-RISC microprocessors.
The PA-8500 was packaged in a smaller 544-pad land grid array (LGA) as the integration of the primary caches on die resulted in the removal of the two 128-bit buses which communicated with the external caches and their associated I/O pads.
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