Decode, and The Instruction Reorder Buffer
During the third stage, the instructions are decoded. In the fourth stage, they are placed in the instruction reorder buffer (IRB). The IRB's purpose is the implement register renaming, out of order execution, speculative execution and to provide a temporary place for results to be stored until the instructions are retired. The IRB determines which instructions are issued during stage five.
The IRB consists of two buffers, one for integer and floating-point instructions, the other for load and store instructions. Some instructions are placed into both buffers. These instructions are branch instructions and certain system instructions. Each buffer has 28 entries. Each buffer can accept up to four instructions per cycle and can issue up to two per a cycle to its functional units.
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