Micro-architectural Choices
- Are the instructions dispatched to a centralized queue or to multiple distributed queues?
- IBM PowerPC processors use queues which are distributed among the different functional units while other Out-of-Order processors use a centralized queue. IBM uses the term reservation stations for their distributed queues.
- Is there an actual results queue or are the results written directly into a register file? For the latter, the queueing function is handled by register maps which hold the register renaming information for each instruction in flight.
- Early Intel out-of-order processors use a results queue called a re-order buffer, while most later Out-of-Order processors use register maps.
- More precisely: Intel P6 family microprocessors have both a ROB re-order buffer and a RAT register map mechanism. The ROB was motivated mainly by branch misprediction recovery.
- The Intel P6 family was among the earliest OoO processors, but was supplanted by the Intel Pentium 4 Willamette microarchitecture. Years later it proved to be a dead end due to thermal issues, forcing Intel to go back to the P6 design and continue from there. The result were the Core, Core 2, Sandy Bridge series of processors and most notably its latest iteration, Ivy Bridge.
Read more about this topic: Out-of-order Execution
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“Our [adult] children have an adult’s right to make their own choices and have the responsibility of living with the consequences. If we make their problems ours, they avoid that responsibility, and we are faced with problems we can’t and shouldn’t solve.”
—Jane Adams (20th century)