NEAT Chipset - History

History

The NEAT chipset descended from the chipset that C&T had developed for IBM XT-compatible systems, which was based around the 82C100 "XT controller" chip. This chip incorporated the functionality of what had been, until its invention, discrete TTL chips on the XT's mainboard, namely:

• the 8284 clock generator
• the 8288 bus controller
• the 8254 Programmable Interval Timer
• the 8255 parallel I/O interface
• the 8259 Programmable Interrupt Controller
• the 8237 DMA controller

The central chip of the NEAT chipset was C&T's 82C206 chip, introduced by C&T in 1986. This chip, like its predecessor the 82C100, provided equivalent functionality to the TTL chips on the PC/AT's mainboard, namely:

• the 82284 clock generator
• the 82288 bus controller
• the 8254 Programmable Interval Timer
• the two 8259 Programmable Interrupt Controllers
• the two 8237 DMA controllers
• the MC146818 NVRAM/RTC chip

This set of components comprised most of the logic (aside from the CPU itself) on a PC/AT-compatible mainboard, and the creation of the 82C206 allowed mainboard manufacturers to significantly reduce the number of components on, and thereby the cost of manufacture of, such mainboards. However, mainboards still required four other chips, in addition to the 82C206. These other chips were buffers and memory controllers. In concert, these five chips were C&T's CS8220 chipset.

The NEAT chipset was the successor to the CS8220. It was officially designated the CS8221. It required only three extra chips in addition to the 82C206.

The successor to the NEAT chipset was the SCAT chipset, which amalgamated all of the chips of the NEAT chipset into a single chip, the 82C836. The 8223 LEAP chipset provided support for LIM EMS 4.0.