NAND Logic - OR

OR

If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1

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