Basic Types of Address Decoding
- Exhaustive — 1:1 mapping of unique addresses to one hardware register (physical memory location)
- Partial — n:1 mapping of n unique addresses to one hardware register. Partial decoding allows a memory location to have more than one address, allowing the programmer to reference a memory location using n different addresses. It may also be done just to simplify the decoding hardware, when not all of the CPU's address space is needed. Synonyms: foldback, multiply mapped, partially mapped.
- Linear — Address lines are used directly without any decoding logic. This is done with devices such as RAMs and ROMs that have a sequence of address inputs, and with peripheral chips that have a similar sequence of inputs for addressing a bank of registers. Linear addressing is rarely used alone (only when there are few devices on the bus, as using purely linear addressing for more than one device usually wastes a lot of address space) but instead is combined with one of the other methods to select a device or group of devices within which the linear addressing selects a single register or memory location.
Read more about this topic: Memory-mapped I/O
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