Low-voltage Positive Emitter-coupled Logic - Implementation

Implementation

ECL is based on an emitter-coupled (long-tailed) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor R_E acts nearly as a current source. The output voltages at the collector load resistors R_C1 and R_C3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors R_E4 and R_E5 do not exist in all versions of ECL. In some cases 50 Ω line termination resistors connected between the bases of the input transistors and −2 V act as emitter resistors.