Larrabee (microarchitecture) - Comparison With Competing Products - Differences With CPUs

Differences With CPUs

The x86 processor cores in Larrabee differed in several ways from the cores in current Intel CPUs such as the Core 2 Duo or Core i7:

• Larrabee's x86 cores were based on the much simpler P54C Pentium design which is still being maintained for use in embedded applications. The P54C-derived core is superscalar but does not include out-of-order execution, though it has been updated with modern features such as x86-64 support, similar to the Bonnell microarchitecture used in Atom. In-order execution means lower performance for individual cores, but since they are smaller, more can fit on a single chip, increasing overall throughput. Execution is also more deterministic so instruction and task scheduling can be done by the compiler.
• Each Larrabee core contained a 512-bit vector processing unit, able to process 16 single precision floating point numbers at a time. This is similar to, but four times larger than, the SSE units on most x86 processors, with additional features like scatter/gather instructions and a mask register designed to make using the vector unit easier and more efficient. Larrabee derives most of its number-crunching power from these vector units.
• Larrabee included one major fixed-function graphics hardware feature: texture sampling units. These perform trilinear and anisotropic filtering and texture decompression.
• Larrabee had a 1024-bit (512-bit each way) ring bus for communication between cores and to memory. This bus can be configured in two modes to support Larrabee products with 16 cores or more, or fewer than 16 cores.
• Larrabee included explicit cache control instructions to reduce cache thrashing during streaming operations which only read/write data once. Explicit prefetching into L2 or L1 cache is also supported.
• Each core supported 4-way interleaved multithreading, with 4 copies of each processor register.

Theoretically Larrabee's x86 processor cores were able to run existing PC software, or even operating systems. A different version of Larrabee might sit in motherboard CPU sockets using QuickPath, but Intel never announced any plans for this. Though Larrabee Native's C/C++ compiler included auto-vectorization and many applications were able to execute correctly after having been recompiled, maximum efficiency was expected to have required code optimization using C++ vector intrinsics or inline Larrabee assembly code. However, as in all GPGPU, not all software would have benefited from utilization of a vector processing unit. One tech journalism site claims that Larrabee graphics capabilities were planned to be integrated in CPUs based on the Haswell microarchitecture.