Joel Mc Cormack - P-machine Design

P-machine Design

In 1979 McCormack was employed by NCR right out of college, and they had developed a Bit slicing implementation of the p-code machine using the Am2900 chip set. This CPU had a myriad of timing and performance problems so McCormack proposed a total redesign of the processor using a programmable logic device based Microsequencer. McCormack left NCR to start a company called Volition Systems but continued the work on the CPU as a contractor. The new CPU used an 80-bit wide microword, so parallelism in the microcode was radically enhanced. There were several loops in the microcode that were a single instruction long and many of the simpler p-code ops took 1 or 2 microcode instructions. With the wide microword and the way the busses were carefully arranged, as well as incrementing memory address registers, the cpu could execute operations inside the ALU while transferring a memory word directly to the onboard stack, or feed one source into the ALU while sending a previously computed register to the destination bus in a single microcycle.

The cpu ran at three different clock speeds (using delay lines for a selectable clock); two bits in the microword selected the cycle time for that instruction. The clocks around 130, 150, and 175 nanoseconds. Newer parts from AMD would have allowed a faster 98 nsec cycle for the fastest instructions, but they didn't come out with a correspondingly faster branch control unit.

There was a separate prefetch/instruction formatting unit (again, using stoppable delay line clocks for synchronization...asynchronous logic allows for skewed timings). It had a 32-bit buffer and could deliver up the next data as a signed byte, unsigned byte, 16-bit word, or "big" operand (the one-or-two byte format where 0..127 was encoded as one byte, and 128..32767 was encoded as two bytes).

There was an onboard stack of 1024 16-bit words, so that both scalars and sets could be operated on there. The top of the stack was actually kept in one of the AMD 2901's registers, so that simple operations like integer addition took a single cycle. before we stole the technique of keeping the top word of the stack in one of the AMD 2901 registers. These often resulted in one fewer microinstructions. (The stack doesn't quite operate this way...it decrements before data is written to it, and increments after data is read.)

Since next-address control and next microcode location were in each wide microword, there was no penalty for any-order execution of the microcode. Thus, we had a table of 256 labels, and the microcode compiler moved the first instruction at each of those labels to the first 256 locations of microcode memory. The only restriction this placed upon the microcode was that if the p-code required more than one microinstruction, then the first microinstruction couldn't have any flow control specified (as it would be filled in with a "goto ).