ICH5
In 2003, and in conjunction with the i865 and i875 northbridges, the ICH5 was created. A SATA host controller was integrated. The ICH5R variant additionally supported RAID 0 on SATA ports. Eight USB-2.0 ports were available. The chip had full support for ACPI 2.0. It had 460 pins.
Since 1999 the 266 MB/s hub interface was assumed to be a bottleneck. In the new chip generation, Intel therefore offered an optional port for a Gigabit Ethernet Controller directly attached to the MCH.
The goal of this CSA technology was to reduce the latencies for Gigabit LAN by direct memory access and to free up bandwidth on the Hub interface between ICH and MCH for non removable disk and PCI data traffic.
Since mid-2004, the large motherboard manufacturers noticed an increased complaint ratio with motherboards equipped with ICH5. A cause was the insufficient ESD tolerance of certain ICH5 steppings.
In particular, when connecting USB devices via front panels, the chips died by discharges of static electricity. Intel reacted to the problem by shipping ICH5 with increased ESD tolerance. Effective ESD preventive measures on USB ports are difficult and costly, since they can impair signal quality of the USB-2.0 high-speed signals. Many motherboard manufacturers had omitted the necessary high-quality safety devices for front panel connectors for cost reasons.
This has the following variants:
- 82801E (C-ICH) Communications
- 82801EB (ICH5) Base
- 82801ER (ICH5R) RAID
- 82801EBM (ICH5-M) Base Mobile
- 6300ESB (ESB) Enterprise Southbridge
Read more about this topic: I/O Controller Hub