History
Achieving confidence that a design is functionally correct continues to become more difficult. To counter these problems, in the late 1980s fast logic simulators and specialized hardware description languages such as Verilog and VHDL became popular. In the 1990s, constrained random simulation methodologies emerged using hardware verification languages such as Vera and e, as well as SystemVerilog (in 2002), to further improve verification quality and time.
Intelligent verification approaches supplement constrained random simulation methodologies, which bases test generation on external input rather than design structure. Intelligent verification is intended to automatically utilize design knowledge during simulation, which has become increasingly important over the last decade due to increased design size and complexity, and a separation between the engineering team that created a design and the team verifying its correct operation.
There has been substantial research into the intelligent verification area, and commercial tools that leverage this technique are just beginning to emerge.
Read more about this topic: Intelligent Verification
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