Intel 8237 - Modes

Modes

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

• Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero.
• Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.
• Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.
• Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.

Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It's used to repeat the last transfer.

The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so.