Features
The S/360-67 included the following extensions in addition to the standard and optional features available on all S/360 systems:
- Dynamic Address Translation (DAT) with support for 24 or 32-bit virtual addresses using segment and page tables (up to 16 segments each containing up to 256 4096 byte pages)
- Extended PSW Mode that enables additional interrupt masking and additional control registers
- High Resolution Interval Timer with a resolution of approximately 13 microseconds
- Reference and change bits as part of storage protection keys
- Extended Direct Control allowing the processors in a duplex configuration to present an external interrupt to the other processor
- Partitioning of the processors, processor storage, and I/O channels in a duplex configuration into two separate subsystems
- Floating Addressing to allow processor storage in a partitioned duplex configuration to be assigned consecutive real memory addresses
- A Channel Controller that allows both processors in a duplex configuration to access all of the I/O channels and that allows I/O interrupts to be presented to either processor independent of what processor initiated the I/O operation
- Simplex configurations can include 7 I/O channels, while duplex configurations can include 14 I/O channels
- Three new supervisor-state instructions: Load Multiple Control (LMC), Store Multiple Control (SMC), Load Real Address (LRA)
- Two new problem-state instructions: Branch and Store Register (BASR), and Branch and Store (BAS)
- Two new program interruptions: Segment translation exception (16) and page translation exception (17)
The S/360-67 operated with a basic internal cycle time of 200 nanoseconds and a basic 750 nanosecond magnetic core storage cycle, the same as the S/360-65. The 200 ns cycle time put the S/360-67 in the middle of the S/360 line in terms of processor speed (3.9 times faster than the Model 30 at 750 ns and 3.7 times slower than the Model 195 at 54 ns). From 1 to 8 bytes (8 data bits and 1 parity bit per byte) could be read or written to processor storage in a single cycle. A 60-bit parallel adder facilitated handling of long fractions in floating-point operations. An 8-bit serial adder enabled simultaneous execution of floating point exponent arithmetic, and also handled decimal arithmetic and variable field length (VFL) instructions.
Read more about this topic: IBM System/360 Model 67
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