Architecture
As designed by Director of Engineering Dr. William L. Gordon, the H200 memory consisted of individually addressed characters, each composed of six data bits, two punctuation bits and a parity bit. The two punctuation bits recorded a word mark and an item mark, while both being set constituted a record mark. The item bit permitted item moves and record moves in addition to word moves (move successive characters one-by-one starting at the addresses given in the instruction, stopping when the relevant punctuation mark was found set in either field).
An instruction consisted of a one-character op-code, up to two operand addresses and an optional single character variant. Usually the op-code character would be word-marked, confirming the end of the previous instruction. An item-marked op-code would be handled differently from normal, and this was used in the emulation of IBM 1401 instructions that were not directly compatible. The first three bits of an operand address could designate one of six index registers that occupied the first 32 addressable memory locations. The other two possible bit patterns indicated no indexing, or indirect addressing.
A Change Address Mode (CAM) instruction switched between 2-, 3- and 4-character address modes. The address mode specified the number of characters needed for each operand address in instructions.
A Change Sequence Mode (CSM) instruction stored the next instruction address in a memory location and loaded the instruction counter from another memory location. This provided a simple switch between threads within a program, similar to the sequence/cosequence behaviour of the Honeywell 800 series.
While the H200 supported operation with just a console, card reader and punch like the IBM 1401, the generic Input-Output instructions also supported line printers and magnetic tape drives.
IO instructions left punctuation bits unchanged, reading or writing only data (and parity) bits into memory, and terminating on any record mark encountered. A record mark could be placed at the end of an input buffer to prevent any buffer overflow, a problem that was to persist in many other systems into the 21st century.
The 200-series IO instructions were a Peripheral Data Transfer (PDT) and a Peripheral Control and Branch (PCB) that explicitly implemented asynchronous IO. The PDT specified a device address, a buffer address and the transfer operation to be started, while the PCB specified a device address, and set the operating mode or tested the status of the device. Both used the format Op-code Address I/O unit address Variant.
Read more about this topic: Honeywell 200
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