Futurebus - Description

Description

Futurebus is described in just a few IEEE standards;

• 896.1-1987 IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus
• 1101-1987 IEEE Standard for Mechanical Core Specifications for Microcomputers Using IEC 603-2 Connectors

Futurebus systems were implemented with 9Ux280 Eurocard mechanics using 96-pin DIN connectors resulting in a backplane that supported both 16 and 32 bit bus widths.

To understand Futurebus+ you need to read many IEEE standards;

• 896.1-1991 IEEE Standard for Futurebus+ — Logical Protocol Specification
• 896.2-1991 IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+
• 896.3-1993 IEEE recommended practice for Futurebus+
• 896.4-1993 IEEE Standard for Conformance Test Requirements for Futurebus+
• 896.5-1993 IEEE Standard for Futurebus+, Profile M (Military)
• 896.6 Futurebus+ telecommunications systems, profile T (telecommunications)
• 896.7 Interconnect between Futurebus+ systems
• 896.8 Small computer expandibility module for Futurebus+ systems, profile D (desktop)
• 896.9-1994 Fault tolerant extensions to the Futurebus+ architecture
• 896.10-1997 Standard for Futurebus+ Spaceborne Systems - Profile S
• 896.11 Standard for IEEE 1355 Links on Futurebus+ Backplane Connector
• 896.12 Standard for Fault Tolerance Classification of Computer-Based Systems
• 1194.1-1991 IEEE Standard for Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits
• 1301 Standard for Metric Equipment Practice for Microcomputers - Coordination Document
• 1301.1-1991 IEEE Standard for a Metric Equipment Practice for Microcomputers—Convection-Cooled with 2 mm Connectors
• 1156.1 Standard Microprocessor Environmental Specifications for Computer Modules
• EIA IS-64 (1991) 2 mm Two-Part Connectors for Use with Printed Boards and Backplanes

896.2 contains three Profiles for target markets, A for general purpose systems, B for an I/O bus, and F for a Futurebus+ will all the options that will make it go fast. Profile A was sponsored by the VMEbus community. Profile B was sponsored by Digital Equipment Corporation and implemented in VAX and Alpha systems as an I/O bus. Profile F was sponsored by John Theus while he worked at Tektronix and was intended for high end workstations.

Futurebus+ supports bus widths from 32 to 256 bits. It is possible to build a board that supports all of these bus widths and will interoperate with boards that only support a subset. Split bus transactions are supported so that slow response to a read or write will not tie up the backplane bus. Cache Coherence, implemented using the MESI protocols, was very complicated but significantly improved performance. Futurebus+ was one of the first open standards to support Live Insertion which allowed boards to be replaced while the system was running.

Futurebus+ boards are 12SUx12SU Hard Metric size defined in the IEEE 1301 standards.

One of the most elegant features of the Futurebus design is its distributed bus arbitration mechanism. See US patent number 5060139 for more information. In the end this was replaced by a central arbiter.