FPGA Prototype - Partitioning Issues

Partitioning Issues

Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs in growing. Hardware platforms are becoming more prominent amongst verification engineers due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior. These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA. The fewer number of FPGAs the design has to be partitioned to reduces the effort from the design engineer. To the right is a picture of a FPGA-based prototyping platform utilizing a dual-FPGA configuration.

System RTL designs or netlist’s will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform. This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test). If the number or partitions can be reduced or the entire design can be placed onto a single FPGA, the implementation of the design onto the prototyping platform becomes easier.