Four-phase Logic - Usage

Usage

Four-phase logic works well; in particular there are no race hazards because every combinational logic gate includes a register. It's worth noting that the layout does not require the bussing of any power supplies - only clock lines are bussed. Also, since the design technique is ratioless (cf. static logic), many designs can use minimum-size transistors.

There are some difficulties:

• The gate output is dynamic. This means that its state is held on capacitance at the gate output. But the output track can cross clock lines and other gate outputs, all of which can change the charge on the capacitor. In order that the gate output voltage remains at some safe 0 or 1 level during the cycle the amount of change has to be calculated and, if necessary, additional (diffusion) capacitance has to be added to the output node.
• For a given supply voltage, process, and clock frequency, the designer has to do some calculations so that the layout engineers can, in turn, do their calculations to work out the 'bulk-up' capacitance needed for each gate. A gate with a lot of capacitance load could need bigger than minimum input transistors (in order that the load could be discharged in time). This in turn increases the load on the gates driving that gate's inputs. So it can happen, especially in high-frequency designs, that the gate sizing keeps on increasing if the speed target is too aggressive.