ETA10 - Description

Description

The ETA10 was a multiprocessor system that supported up to eight CPUs. Each CPU was similar to that of a two-lane Cyber 205. One of the main innovations of the ETA10 was how the CPU was implemented: the CPU was made of 250 CMOS gate array integrated circuits mounted on a 44-layer printed circuit board (PCB). Each gate array contained 20,000 gates and was fabricated using 1.25-micrometre (μm) technology that was accessible from the VHSIC program at Honeywell. In contrast, mainstream commercial technology at the time was in the 3 to 5 μm range.

CMOS circuitry, which was not typically used in vector supercomputer CPUs at the time, was chosen because of the high density achievable, which reduces both the on-chip and off-chip delay. The CPU delays were managed through careful tuning of each PCB manufactured in conjunction with the logic technology and incorporated two key technologies known as JTAG and BIST. The gate arrays were designed using a combination of internally developed simulator and placement tools, and one of the first commercial electronic design automation tools (an application for schematic capture) from Mentor Graphics. Prior to the use of schematic capture at ETA, designers used textual netlists to describe the interconnection of the logic circuits.

However, CMOS circuitry at that time was significantly slower than that of bipolar circuitry, especially the emitter-coupled logic that was widely used in vector supercomputer CPUs at the time. To compensate for this, the CPU was immersed in -196.15 °C liquid nitrogen for cooling. Although such cooling could potentially speed up the CMOS logic by a factor of four, in practice the liquid nitrogen cooling yielded an approximately twofold speed increase over air-cooled systems. However, because liquid nitrogen cooling yielded only marginal performance benefits, none of the ETA10 systems used such cooling for either the local or shared memories. It is of particular note that in order for this type of cooling to be effective, a closed-loop system was required. ETA had to innovate to make this possible, since there were not any commercially available solutions in the market. The 44-layer PCB was also innovative, and ETA had to develop new processes to manufacture it.

Each CPU had its own 4 million word local memory built from SRAM ICs. Each CPU is also connected to a 256 million word shared memory built from DRAM ICs. In addition to these memories, there is a communication buffer used for CPU synchronization and other multiprocessor-related protocol communication. I/O was facilitated by one to eighteen I/O processors that each have a direct path to the shared memory. The ETA10 used fiber-optic lines for communication between the CPUs and I/O devices, a novel approach for systems interconnection in the 1980s.