Cache Entry Structure
Cache row entries usually have the following structure:
| tag | data block | flag bits |
The data block (cache line) contains the actual data fetched from the main memory. The tag contains (part of) the address of the actual data fetched from the main memory. The flag bits are discussed below.
The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache. (The number of tag and flag bits is irrelevant to this calculation, although it does affect the physical area of a cache).
An effective memory address is split (MSB to LSB) into the tag, the index and the block offset.
| tag | index | block offset |
The index describes which cache row (which cache line) that the data has been put in. The index length is bits. The block offset specifies the desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is bits. The tag contains the most significant bits of the address, which are checked against the current row (the row has been retrieved by index) to see if it is the one we need or another, irrelevant memory location that happened to have the same index bits as the one we want. The tag length in bits is .
Some authors refer to the block offset as simply the "offset" or the "displacement".
Read more about this topic: CPU Cache
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