Cyberplus or Advanced Flexible Processor (AFP)
Each Cyberplus (aka Advanced Flexible Processor, AFP) is a 16-bit processor with optional 64-bit floating point capabilities and has 256 K or 512 K words of 64-bit memory. The AFP was the successor to the Flexible Processor (FP), whose design development started in 1972 under black-project circumstances targeted at processing radar and photo image data. The FP control unit had a hardware network for conditional microinstruction execution, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I/O conditions, and loop control: an ancestor to the ARM architecture.
At least 21 Cyberplus multiprocessor installations were operational in 1986. These parallel processing systems include from 1 to 256 Cyberplus processors providing 250 MFLOPS each, which are connected to an existing Cyber system via a direct memory interconnect architecture (MIA), this was available on NOS 2.2 for the Cyber 170/835, 845, 855 and 180/990 models.
- Each physical Cyberplus processor unit was
- 348 cm wide (465 cm with floating point unit)
- 161 cm deep
- 490 cm high
- 1000 kg weight
- Software that was bundled with the Cyberplus was
- system software
- FORTRAN cross compiler
- MICA (Machine Instruction Cross Assembler)
- Load File Builder Utility
- ECHOS (simulator)
- Debug facility
- Dump utility
- Dump analyzer utility
- Maintenance software
Some sites using the Cyberplus were the University of Georgia and the Gesellschaft für Trendanalysen (GfTA) (Association for Trend Analyses) in Germany.
A fully configured 256 processor Cyberplus system would have a theoretical performance of 64 GFLOPS and would weigh 256 tonnes.
Read more about this topic: CDC Cyber
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