CDC Cyber - Cyber 70 and 170 Series

Cyber 70 and 170 Series

The Cyber 70 and 170 architectures were successors to the earlier CDC 6600 and CDC 7600 series and therefore shared almost all of the earlier architecture's characteristics. The Cyber-70 series was a minor upgrade from the earlier systems. The Cyber-170 series represented CDCs move from discrete electronic components and core memory to integrated circuits and semiconductor memory. The Cyber-170/700 series was a late-1970s refresh of the Cyber-170 line.

The central processor (CPU) and central memory (CM) operated in units of 60-bit words. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits. The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which was semiconductor memory in this series. The central processor had no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.

A Cyber 170-series system consisted of one or two CPUs that ran at either 25 or 40 MHz, and was equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed I/O. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating point divides), the higher end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) were equipped with 8 or 12 words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which was usually called in-stack) would run without referencing main memory for instruction fetch. The lower-end models did not contain an instruction stack. However since up to four instructions were packed into each 60-bit word, some degree of prefetching was inherent in the design.

As with predecessor systems, the Cyber 170 series had eight 18-bit address registers (A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7). Seven of the A registers were tied to their corresponding X register. Setting A1 through A5 read that address and fetched it into the corresponding X1 through X5 register. Likewise, setting register A6 or A7 wrote the corresponding X6 or X7 register to central memory at the address written to the A register. A0 was effectively a scratch register.

The higher end CPUs consisted of multiple functional units (e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allowed assembly programmers to minimize the effects of the system's slow memory fetch time by pre-fetching data from central memory well before that data was needed. By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch could be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer could write extremely efficient code that made the most of the power of the hardware.

The peripheral processor subsystem used a technique known as barrel and slot to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware multiprogramming. The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP had access to all I/O channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacked, for example, extensive arithmetic capabilities and did not run user code; the peripheral processor subsystem's purpose was to process I/O and thereby free the more powerful central processor unit(s) to running user computations.

A feature of the 'lower Cyber' CPUs was the Compare Move Unit (CMU). It provided four additional instructions intended to aid text processing applications. In an unusual departure from the rest of the 15- and 30-bit instructions, these were 60-bit instructions (3 actually used all 60 bits, the other used 30 bits, but its alignment required 60 bits to be used). The instructions were move a short string, move a long string, compare strings, and compare a collated string. They operated on 6-bit fields (numbered 1 through 10) in central memory. For example, a single instruction could specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9". The CMU hardware was not included in the higher-end Cyber CPUs, because handcoded loops could run as fast or faster than the CMU instructions.

Later systems typically ran CDC's NOS (Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982. Besides NOS, the only other operating systems commonly used on the 170 series was NOS/BE or its predecessor SCOPE, a product of CDC's Sunnyvale division. These operating systems provided time sharing of batch and interactive applications. The predecessor to NOS was Kronos which was in common use up until 1975 or so. Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems than convert their applications. Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility.