CDC 6000 Series - Central Processor

Central Processor

The central processor was the high-speed arithmetic unit that functioned as the workhorse of the computer. It performed the addition, subtraction, and logical operations and all of the multiplication, division, incrementing, indexing, and branching instructions for user programs. Note that in the CDC 6000 architecture, the central processing unit performed no I/O operations. I/O was totally asynchronous, and performed by peripheral processors.

A 6000 series CPU contained 24 operating registers, designated X0-X7, A0-A7, and B0-B7. The eight X registers were each 60 bits long, and used for most data manipulation—both integer and floating point. The eight B registers were 18 bits long, and generally used for indexing and address storage. Register B0 was hard-wired to always return 0. By software convention, register B1 was generally set to 1. (This often allowed the use of 15-bit instructions instead of 30-bit instructions.) The eight 18-bit A registers were 'coupled' to their corresponding X registers in an interesting way: setting an address into any of registers A1 through A5 caused a memory load of the contents of that address into the corresponding X registers. Likewise, setting an address into registers A6 and A7 caused a memory store into that location in memory from X6 or X7. Registers A0 and X0 were not coupled in this way, so could be used as scratch registers. However A0 and X0 were used when addressing CDCs Extended Core Storage (ECS).

Instructions were either 15 or 30 bits long, so there could be up to 4 instructions per 60-bit word. The op codes were 6 bits long. The remainder of the instruction was either three 3-bit register fields (two operands and one result), or two registers with an 18-bit immediate constant. All instructions were 'register to register'. For example the following COMPASS code loads two values from memory, performs a 60-bit integer add, then stores the result:

The central processor used in the CDC 6400 series contained a unified arithmetic element which performed one machine instruction at a time. Depending on instruction type, an instruction could take anywhere from a relatively fast 5 clock cycles (18-bit integer arithmetic) to as many as 68 clock cycles (60-bit population count). The CDC 6500 was identical to the 6400, but included two identical 6400 CPUs. Thus the CDC 6500 could nearly double the computational throughput of the machine.

The CDC 6600 computer, like the CDC 6400, has just one central processor. However, its central processor offered much greater efficiency. The processor was divided into 10 individual functional units, each of which was designed for a specific type of operation. The function units provided were: branch, Boolean, shift, long integer add, floating-point add, floating-point divide, two floating-point multipliers, and two increment (18-bit integer add) units. Functional unit latencies were between a very fast 3 clock cycles (increment add) and 29 clock cycles (floating-point divide).

The 6600 processor could issue a new instruction every clock cycle, assuming that various processor (functional unit, register) resources were available. These resources were kept track of by a scoreboard mechanism. Also contributing to keeping the issue rate high was an instruction stack, which cached the contents of several instruction words. Small loops could reside entirely within the stack, eliminating memory latency from instruction fetches.

Both the 6400 and 6600 CPUs had a cycle time of 100 ns (10 MHz). Due to the serial nature of the 6400 CPU, its exact speed was heavily dependent on instruction mix, but generally around 1 MIPS. Floating-point additions were fairly fast at 11 clocks, however floating-point multiplication was very slow at 57 clocks. Thus its floating point speed would depend heavily on the mix of operations and could be under 200 kFLOPS. The 6600 was, of course, much faster. With good compiler instruction scheduling, the machine could approach its theoretical peak of 10 MIPS. Floating-point additions took 4 clocks, and floating-point multiplies took 10 clocks (but there were two multiply functional units, so two operations could be processing at the same time.) The 6600 could therefore have a peak floating point speed of 2-3 MFLOPS.

The CDC 6700 computer combined the best features of the other three computers. Like the CDC 6500, it had two central processors. One was a CDC 6400/CDC 6500 central processor with the unified arithmetic section; the other was the more efficient CDC 6600 central processor. The combination made the CDC 6700 the fastest and the most powerful of the four CDC 6000 series.