Architecture
The lower 3000 CPU was a 24-bit architecture: instructions were 24 bits in length, as were the two operand registers A and Q. There were 4 index registers of 15 bits, B0 through B3, though B0 is always zero (zero when read; writes don't affect the value). There was no status (flags or condition code) register. Up to 32,768 (24-bit) words of core memory could be directly addressed, and multiple banks could be switched in. Two or three memory bank configurations were the most common.
Each instruction contained 6 bits of opcode, 1 bit specifying whether indirect addressing used, 2 bits of index register address and 15 bits of address.
Arithmetic was ones' complement, so there were two forms of zero: positive zero and negative zero. The A and Q register could function as a combined 48-bit register for certain arithmetic instructions. The E register had 48 bits.
The 3300 CPU could execute around 1 million instructions per second (1 MIP), giving it supercomputer status in 1965.
Read more about this topic: CDC 3000
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