Carry-lookahead Adder - Implementation Details

Implementation Details

For each bit in a binary sequence to be added, the Carry Look Ahead Logic will determine whether that bit pair will generate a carry or propagate a carry. This allows the circuit to "pre-process" the two numbers being added to determine the carry ahead of time. Then, when the actual addition is performed, there is no delay from waiting for the ripple carry effect (or time it takes for the carry from the first Full Adder to be passed down to the last Full Adder). Below is a simple 4-bit generalized Carry Look Ahead circuit that combines with the 4-bit Ripple Carry Adder we used above with some slight adjustments:

For the example provided, the logic for the generate (g) and propagate (p) values are given below. Note that the numeric value determines the signal from the circuit above, starting from 0 on the far left to 3 on the far right:

Substituting into, then into, then into yields the expanded equations:

To determine whether a bit pair will generate a carry, the following logic works:

To determine whether a bit pair will propagate a carry, either of the following logic statements work:

The reason why this works is based on evaluation of . The only difference in the truth tables between and is when both and are 1. However, if both and are 1, then the term is 1 (since its equation is ), and the term becomes irrelevant. The XOR is used normally within a basic full adder circuit; the OR is an alternate option (for a carry lookahead only) which is far simpler in transistor-count terms.

The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each CLA Logic circuit produce a propagate and generate signal to a higher-level CLA Logic circuit. The group propagate and group generate for a 4-bit CLA are:

Putting 4 4-bit CLAs together yields four group propagates and four group generates. A Lookahead Carry Unit (LCU) takes these 8 values and uses identical logic to calculate in the CLAs. The LCU then generates the carry input for each of the 4 CLAs and a fifth equal to .

The calculation of the gate delay of a 16-bit adder (using 4 CLAs and 1 LCU) is not as straight forward as the ripple carry adder. Starting at time of zero:

• calculation of and is done at time 1
• calculation of is done at time 3
• calculation of the is done at time 2
• calculation of the is done at time 3
• calculation of the inputs for the CLAs from the LCU are done at
  • time 0 for the first CLA
  • time 5 for the second CLA
  • time 5 for the third & fourth CLA
• calculation of the are done at
  • time 4 for the first CLA
  • time 8 for the second CLA
  • time 8 for the third & fourth CLA
• calculation of the final carry bit is done at time 5

The maximum time is 8 gate delays (for ). A standard 16-bit ripple carry adder would take 31 gate delays.