History
One of the earliest examples of a barrel processor was the I/O processing system in the CDC 6000 series supercomputers. These executed one instruction (or a portion of an instruction) from each of 10 different virtual processors (called peripheral processors) before returning to the first processor.
Barrel processors have also been used as large-scale central processors. The Tera MTA (1988) was a large-scale barrel processor design with 128 threads per core. The MTA architecture has seen continued development in successive products, such as the YarcData uRiKA, introduced in 2012 and targeted at data-mining applications.
Barrel processors are also found in embedded systems, where they are particularly useful for their deterministic real-time thread performance. An example is the XMOS XCore XS1 (2007), a four-stage barrel processor with eight threads per core. The XS1 is found in Ethernet, USB, audio, and control devices, and other applications where I/O performance is critical. Barrel processors have also been used in specialized devices such as the 8-thread Ubicom IP3023 network I/O processor (2004).
Read more about this topic: Barrel Processor
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