BACPAC - BACPAC Outputs

BACPAC Outputs

Delay analysis

• Chip area
• Maximum clock frequency - how fast the chip can run
• Optimized device sizes - estimated devices sizes to make it run this fast
• Interconnect RC
• Average wirelength (local & global)
• Ratio of wire delay to gate delay

Noise analysis

• Clock frequency with noise
• Newly optimized device sizes for the clock distribution network
• Ratio of wire delay to gate delay

Wirability analysis

• Wiring capacity
• Wiring requirements (global & local),
• Wiring needs for clock distribution
• Wiring needs for the power distribution network

Power analysis

• Total power consumption, diivided into sub-categories:
  • Clock (power needed to distribute the clock across the chip)
  • I/O (power needed to get needed signals on and off the chip)
  • memory (power needed to retain and access data in the internal memories)
  • global wiring (power dissipated in the global wiring)
  • logic (power dissipated in the logic gates themselves)
  • short-circuit (power wasted inside the gates from pull-up and pull down transistors fighting each other during switching)
  • leakage (power that flows through the gate even when it is not switching)

Yield analysis

• Projected yields for excellent, average, and poor process control using a negative binomial yield mode