ARM Cortex-A9 MPCore - Overview

Overview

Key features of the Cortex-A9 core are:

• Out-of-order speculative issue superscalar execution pipeline giving 2.50 DMIPS/MHz/core.
• NEON SIMD instruction set extension performing up to 16 operations per instruction (optional).
• High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional).
• Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
• TrustZone security extensions.
• Jazelle DBX support for Java execution.
• Jazelle RCT for JIT compilation.
• Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution.
• L2 cache controller (0-4 MB).
• Multi-core processing.

ARM states that the TSMC 40G hard macro implementation typically operating at 2 GHz; a single core (excluding caches) occupies less than 1.5 mm2 when designed in a TSMC 65 nanometer (nm) generic process and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core.